[Skyeye-developer] Fwd: SF.net SVN: skyeye: [269]
skyeye-v1/trunk/arch/mips
kang shuo
blackfin.kang at gmail.com
Sat Jul 7 22:27:35 CST 2007
---------- Forwarded message ----------
From: kangsh at users.sourceforge.net <kangsh at users.sourceforge.net>
Date: Jul 7, 2007 10:11 PM
Subject: SF.net SVN: skyeye: [269] skyeye-v1/trunk/arch/mips
To: blackfin.kang at gmail.com
Revision: 269
http://skyeye.svn.sourceforge.net/skyeye/?rev=269&view=rev
Author: kangsh
Date: 2007-07-07 07:11:26 -0700 (Sat, 07 Jul 2007)
Log Message:
-----------
Big improvement for mips simulation, add more register and instruction
Modified Paths:
--------------
skyeye-v1/trunk/arch/mips/common/cp0.c
skyeye-v1/trunk/arch/mips/common/dcache.c
skyeye-v1/trunk/arch/mips/common/decoder.c
skyeye-v1/trunk/arch/mips/common/emul.c
skyeye-v1/trunk/arch/mips/common/emul.h
skyeye-v1/trunk/arch/mips/common/instr.h
skyeye-v1/trunk/arch/mips/common/mips_arch_interface.c
skyeye-v1/trunk/arch/mips/common/mipsio.c
skyeye-v1/trunk/arch/mips/common/mipsmem.c
skyeye-v1/trunk/arch/mips/common/tlb.c
skyeye-v1/trunk/arch/mips/mach/skyeye_mach_au1100.c
Modified: skyeye-v1/trunk/arch/mips/common/cp0.c
===================================================================
--- skyeye-v1/trunk/arch/mips/common/cp0.c 2007-07-07 14:07:00
UTC (rev 268)
+++ skyeye-v1/trunk/arch/mips/common/cp0.c 2007-07-07 14:11:26
UTC (rev 269)
@@ -186,6 +186,8 @@
}
case CTCz:
{
+ process_reserved_instruction(mstate);
+
// Move Control To Coprocessor
return nothing_special;
}
@@ -197,6 +199,7 @@
case BCzT:
case BCzFL:
case BCzTL:
+
process_reserved_instruction(mstate);
return nothing_special;
default:
process_reserved_instruction(mstate);
@@ -210,4 +213,32 @@
}
return nothing_special;
}
+int
+decode_cop1(MIPS_State* mstate, Instr instr)
+{
+ fprintf(stderr, "in %s\n", __FUNCTION__);
+
+ // CP0 is usable in kernel more or when the CU bit in SR is set.
+ if (!(mstate->mode & kmode) && !bit(mstate->cp0[SR], SR_CU0))
+ process_coprocessor_unusable(mstate, 0);
+
+ /* Only COP0, MFC0 and MTC0 make sense, although the R3K
+ * manuals say nothing about handling the others.
+ */
+
+ switch (fmt(instr)){
+ case CF:
+ if(fs(instr) == 0)
+ mstate->gpr[ft(instr)] = mstate->fir;
+ else
+ fprintf(stderr, "Not implementation
for CFC1 instruction\n");
+ break;
+
+ default:
+ process_reserved_instruction(mstate);
+ break;
+ }
+ return nothing_special;
+}
+
Modified: skyeye-v1/trunk/arch/mips/common/dcache.c
===================================================================
--- skyeye-v1/trunk/arch/mips/common/dcache.c 2007-07-07 14:07:00
UTC (rev 268)
+++ skyeye-v1/trunk/arch/mips/common/dcache.c 2007-07-07 14:11:26
UTC (rev 269)
@@ -153,7 +153,7 @@
* improvements steming from the fact that bit field extraction on variable
* boundaries is slow.
*/
-
+#if 0
void
load(MIPS_State* mstate, VA va, PA pa, UInt32* x, int size)
{
@@ -230,7 +230,20 @@
}
}
}
+#endif
+void
+load(MIPS_State* mstate, VA va, PA pa, UInt32* x, int size)
+{
+ // to generate the time out interrupt
+
+ UInt32 addr = bits(pa, 31, 0);
+
+ int i;
+
+ // A direct memory access.
+ return mips_mem_read(pa, x, size);
+}
/* Store data to the virtual address (va). The address translation has already
* been performed and the physical address is (pa). The coherency algorithm to
* use is encoded in high-order bits of (pa) using the same encoding as that
@@ -240,19 +253,21 @@
* steming from the fact that bit field extraction on variable boundaries is
* slow.
*/
-
+#if 0
void
store(MIPS_State* mstate, UInt32 data, VA va, PA pa, int size)
{
UInt32 addr=bits(pa, 31, 0);
UInt32 x = data;
+
int ca = coherency_algorithm(pa);
// Anthony Lee 2007-01-30 : no {} ???
- if (ca == 0x5) //Shi yang uncached area
+ if (ca == 0x5) //Shi yang uncached area
mips_mem_write(pa, &data, size);
return; //Shi yang 2006-08-28
+
// A cached memory access.
UInt32 index = Dcache_index(pa); //Shi yang 2006-08-15
@@ -305,11 +320,21 @@
}
case 4:
{
- //*x = cachelinedata;
- *cachelinedata = x;
+ *x = cachelinedata;
mips_mem_write(pa, &data, size);
break;
}
}
}
+#endif
+/*
+ * simple implementation for store function written by michael.kang
+ */
+
+void
+store(MIPS_State* mstate, UInt32 data, VA va, PA pa, int size) {
+ UInt32 addr=bits(pa, 31, 0);
+ UInt32 x = data;
+ return mips_mem_write(pa, &data, size);
+}
Modified: skyeye-v1/trunk/arch/mips/common/decoder.c
===================================================================
--- skyeye-v1/trunk/arch/mips/common/decoder.c 2007-07-07 14:07:00
UTC (rev 268)
+++ skyeye-v1/trunk/arch/mips/common/decoder.c 2007-07-07 14:11:26
UTC (rev 269)
@@ -92,6 +92,21 @@
return nothing_special;
}
+ case MOVZ:
+ {
+ if(!mstate->gpr[rt(instr)])
+ mstate->gpr[rd(instr)]
= mstate->gpr[rs(instr)];
+ return nothing_special;
+
+ }
+ case MOVN:
+ {
+ if(mstate->gpr[rt(instr)])
+
mstate->gpr[rd(instr)] = mstate->gpr[rs(instr)];
+ return nothing_special;
+
+ }
+
case JR:
{
// Jump Register
@@ -131,7 +146,7 @@
{
// Synchronize
//Fix me Shi yang 2006-08-08
- process_reserved_instruction(mstate);
+ //process_reserved_instruction(mstate);
return nothing_special;
}
case MFHI:
@@ -379,7 +394,10 @@
case TNE:
{
// Trap If Not Equal
- process_reserved_instruction(mstate);
+ if( mstate->gpr[rs(instr)] !=
mstate->gpr[rt(instr)])
+ fprintf(stderr,"trap
happed in %s.\n", __FUNCTION__);
+ //process_reserved_instruction(mstate);
+
return nothing_special;
}
case DSLL:
@@ -422,8 +440,8 @@
// Reserved instruction
process_reserved_instruction(mstate);
return nothing_special;
- }
- }
+ }// switch (function(instr)) {
+ }//case SPECIAL:
case REGIMM:
{
@@ -544,7 +562,7 @@
process_reserved_instruction(mstate);
return nothing_special; //Fix
me. Shi yang 2006-08-09
}
- }
+ }//case REGIMM:
case J:
{
// Jump
@@ -710,9 +728,9 @@
}
case COP1:
{
+ return decode_cop1(mstate, instr);
// Coprocessor 1 Operation
- process_reserved_instruction(mstate);
- return nothing_special;
+ //process_reserved_instruction(mstate);
}
case COP2:
{
@@ -767,6 +785,24 @@
process_reserved_instruction(mstate);
return nothing_special;
}
+ case SPECIAL2:
+ {
+
+ switch (function(instr)) {
+ case FMUL:
+ {
+ // Branch On Less Than Zero
+ mstate->gpr[rd(instr)] =
mstate->gpr[rs(instr)] * mstate->gpr[rt(instr)];
+ return nothing_special;
+ }
+ default:
+ // Load Doubleword Right
+ process_reserved_instruction(mstate);
+ return nothing_special;
+ }
+ }
+
+
case LB:
{
// Load Byte
@@ -991,7 +1027,12 @@
case LL:
{
// Load Linked
- process_reserved_instruction(mstate);
+ int va = mstate->gpr[base(instr)] + offset(instr);
+ PA pa = translate_vaddr(mstate, va, data_load);
+ int data;
+ mips_mem_read(pa, &data, 4);
+ mstate->gpr[rt(instr)] = data;
+ //process_reserved_instruction(mstate);
return nothing_special;
}
case LWC1:
@@ -1032,7 +1073,14 @@
case SC:
{
// Store Conditional
- process_reserved_instruction(mstate);
+ int va = mstate->gpr[base(instr)] + offset(instr);
+ PA pa = translate_vaddr(mstate, va, data_load);
+ int data;
+ data = mstate->gpr[rt(instr)];
+ mips_mem_write(pa, &data, 4);
+ mstate->gpr[rt(instr)] = 1;
+
+ //process_reserved_instruction(mstate);
return nothing_special;
}
case SWC1:
Modified: skyeye-v1/trunk/arch/mips/common/emul.c
===================================================================
--- skyeye-v1/trunk/arch/mips/common/emul.c 2007-07-07 14:07:00
UTC (rev 268)
+++ skyeye-v1/trunk/arch/mips/common/emul.c 2007-07-07 14:11:26
UTC (rev 269)
@@ -1,4 +1,28 @@
#include "emul.h"
+/*
+ mips_regdefs.c - necessary mips definition for skyeye debugger
+ Copyright (C) 2003 Skyeye Develop Group
+ for help please send mail to <skyeye-developer at lists.sf.linuxforum.net>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA
+
+*/
+/*
+ * 07/06/2007 Michael.Kang <blackfin.kang at gmail.com>
+ */
+#include <stdio.h>
#include <stdlib.h>
extern MIPS_State* mstate;
@@ -178,6 +202,8 @@
void
process_reserved_instruction(MIPS_State* mstate)
{
+ fprintf(stderr,"In %s,pc=0x%x\n", __FUNCTION__, mstate->pc);
+ skyeye_exit(-1);
process_exception(mstate, EXC_RI, common_vector);
}
Modified: skyeye-v1/trunk/arch/mips/common/emul.h
===================================================================
--- skyeye-v1/trunk/arch/mips/common/emul.h 2007-07-07 14:07:00
UTC (rev 268)
+++ skyeye-v1/trunk/arch/mips/common/emul.h 2007-07-07 14:11:26
UTC (rev 269)
@@ -152,6 +152,7 @@
VA pc; // Program Counter
UInt32 gpr[32]; // General Purpose Registers
UInt32 fpr[32]; // Floating-Point General Purpose Registers
+ UInt32 fir,fcsr; // Floating-point implementation
register and control-status register
UInt32 cp0[32]; // CP0 Registers
UInt32 cp1[32]; // CP1 Registers
UInt32 hi, lo; // Multiply and Divide Registers
Modified: skyeye-v1/trunk/arch/mips/common/instr.h
===================================================================
--- skyeye-v1/trunk/arch/mips/common/instr.h 2007-07-07 14:07:00
UTC (rev 268)
+++ skyeye-v1/trunk/arch/mips/common/instr.h 2007-07-07 14:11:26
UTC (rev 269)
@@ -64,6 +64,7 @@
#define DADDIU 031
#define LDL 032
#define LDR 033
+#define SPECIAL2 034
// reserved = 034,
// reserved = 035,
// reserved = 036,
@@ -115,8 +116,10 @@
#define SRLV 006
#define SRAV 007
-#define JR 010
+#define JR 010
#define JALR 011
+#define MOVZ 012
+#define MOVN 013
// reserved = 012,
// reserved = 013,
#define SYSCALL 014
@@ -336,5 +339,7 @@
#define less 2
#define signalling 3
+
+#define CF 2
#endif //end of _INSTR_H_
Modified: skyeye-v1/trunk/arch/mips/common/mips_arch_interface.c
===================================================================
--- skyeye-v1/trunk/arch/mips/common/mips_arch_interface.c
2007-07-07 14:07:00 UTC (rev 268)
+++ skyeye-v1/trunk/arch/mips/common/mips_arch_interface.c
2007-07-07 14:11:26 UTC (rev 269)
@@ -21,6 +21,8 @@
MIPS_State* mstate;
static char *arch_name = "mips";
mips_mem_config_t mips_mem_config;
+extern mips_mem_state_t mips_mem;
+extern FILE *skyeye_logfd;
extern int trace_level;
extern UInt8* mem_bunks;
extern void mips_mem_reset ();
@@ -137,6 +139,7 @@
break;
}
default:
+ fprintf(stderr, "unimplemented write for size
%d in %s\n", len, __FUNCTION__);
break;
}
return;
@@ -296,7 +299,7 @@
Instr instr;
//instr = fetch(mstate, mstate->pc, pa);
mips_mem_read(pa, &instr, 4);
- fprintf(stderr, "KSDBG:instr=0x%x,pa=0x%x, va=0x%x\n", instr, pa, va);
+ fprintf(skyeye_logfd, "KSDBG:instr=0x%x,pa=0x%x, va=0x%x,
sp=0x%x, ra=0x%x,ra_mem=0x%x\n", instr, pa, va, mstate->gpr[29],
mstate->gpr[31],mips_mem.rom[0][(0x3c5ed8 >> 2)]);
int next_state = decode(mstate, instr);
switch (mstate->pipeline) {
Modified: skyeye-v1/trunk/arch/mips/common/mipsio.c
===================================================================
--- skyeye-v1/trunk/arch/mips/common/mipsio.c 2007-07-07 14:07:00
UTC (rev 268)
+++ skyeye-v1/trunk/arch/mips/common/mipsio.c 2007-07-07 14:11:26
UTC (rev 269)
@@ -1,3 +1,26 @@
+/*
+ mipsio.c - necessary arm definition for skyeye debugger
+ Copyright (C) 2003-2007 Skyeye Develop Group
+ for help please send mail to <skyeye-developer at lists.sf.linuxforum.net>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA
+
+*/
+/*
+ * 06/07/2006 Michael.Kang <blackfin.kang at gmail.com>
+ */
#include "types.h"
#include "emul.h"
@@ -10,8 +33,12 @@
{
if (skyeye_config.mach->mach_io_read_byte)
return skyeye_config.mach->mach_io_read_byte(mstate, addr);
- else
- return 0;
+ else{
+ fprintf(stderr, "io_read_byte is not initialized,in
%s \n", __FUNCTION__);
+
+ skyeye_exit(-1);
+ return 0; /* never executed */
+ }
}
UInt32
@@ -19,8 +46,12 @@
{
if (skyeye_config.mach->mach_io_read_halfword)
return skyeye_config.mach->mach_io_read_halfword(mstate, addr);
- else
- return 0;
+ else{
+ fprintf(stderr, "io_read_halfword is not initialized,
in %s\n", __FUNCTION__);
+
+ skyeye_exit(-1);
+ return 0; /* never executed */
+ }
}
UInt32
@@ -29,14 +60,18 @@
if (skyeye_config.mach->mach_io_read_word)
return skyeye_config.mach->mach_io_read_word(mstate, addr);
- else
- return 0;
+ else{
+ fprintf(stderr, "io_read_word is not initializedin
%s\n", __FUNCTION__);
+ skyeye_exit(-1);
+ return 0; /* never executed */
+ }
}
UInt64
mips_io_read_doubleword(UInt32 addr)
{
- return 0;
+ fprintf(stderr, "io_read_doubleword is not initializedin
%s\n", __FUNCTION__);
+ skyeye_exit(-1);
}
void
@@ -45,6 +80,10 @@
if (skyeye_config.mach->mach_io_write_byte)
skyeye_config.mach->mach_io_write_byte(mstate, addr, data);
+ else{
+ fprintf(stderr, "io_write_byte is not initializedin
%s\n", __FUNCTION__);
+ skyeye_exit(-1);
+ }
}
void
@@ -53,6 +92,10 @@
if (skyeye_config.mach->mach_io_write_halfword)
skyeye_config.mach->mach_io_write_halfword(mstate, addr, data);
+ else{
+ fprintf(stderr, "io_write_halfword is not
initializedin %s\n", __FUNCTION__);
+ skyeye_exit(-1);
+ }
}
void
@@ -61,10 +104,16 @@
if (skyeye_config.mach->mach_io_write_word)
skyeye_config.mach->mach_io_write_word(mstate, addr, data);
+ else{
+ fprintf(stderr, "io_write_word is not initializedin
%s\n", __FUNCTION__);
+ skyeye_exit(-1);
+ }
}
void
mips_io_write_doubleword(UInt32 addr, UInt32 data)
{
+ fprintf(stderr, "io_write_doubleword is not initializedin
%s\n", __FUNCTION__);
+ skyeye_exit(-1);
}
Modified: skyeye-v1/trunk/arch/mips/common/mipsmem.c
===================================================================
--- skyeye-v1/trunk/arch/mips/common/mipsmem.c 2007-07-07 14:07:00
UTC (rev 268)
+++ skyeye-v1/trunk/arch/mips/common/mipsmem.c 2007-07-07 14:11:26
UTC (rev 269)
@@ -9,6 +9,8 @@
extern mips_mem_config_t mips_mem_config;
extern MIPS_State* mstate;
+extern FILE * skyeye_logfd;
+
void mips_mem_reset ()
{
int i, num, bank;
@@ -142,6 +144,7 @@
mips_mem_config.mem_banks)][(addr -
mips_global_mbp->
addr) >> 2];
+// fprintf(skyeye_logfd,"after real_read_word addr=0x%x,pc=0x%x,
data=0x%x\n", addr, mstate->pc, mips_mem.rom[0][(0x3c5ed8 >> 2)]);
return data;
}
@@ -167,8 +170,7 @@
UInt32 offset;
temp = &(mips_mem.rom[mips_global_mbp -
mips_mem_config.mem_banks][(addr -
- mips_global_mbp->
- addr) >> 2]);
+ mips_global_mbp->addr) >> 2]);
offset = (((UInt32) mstate->bigendSig * 3) ^ (addr & 3)) << 3;
//Shi yang 2006-08-18
@@ -194,16 +196,17 @@
void
-mips_real_write_word ( UInt32 addr, UInt32 data)
+mips_real_write_word (UInt32 addr, UInt32 data)
{
UInt32 *temp;
-
+ //fprintf(skyeye_logfd,"before addr=0x%x,pc=0x%x,data=0x%x\n",
addr, mstate->pc, mips_mem.rom[0][(0x3c5ed8 >> 2)]);
temp = &(mips_mem.rom[mips_global_mbp -
- mips_mem_config.mem_banks][(addr -
- mips_global_mbp->
- addr) >> 2]);
+ mips_mem_config.mem_banks]
+ [(addr - mips_global_mbp->addr) >> 2]);
*temp = data;
+ //fprintf(skyeye_logfd,"after addr=0x%x,pc=0x%x, data=0x%x\n",
addr, mstate->pc, mips_mem.rom[0][(0x3c5ed8 >> 2)]);
+
}
void
@@ -329,7 +332,7 @@
if (mips_global_mbp && mips_global_mbp->write_byte) {
mips_global_mbp->write_byte (addr, v);
} else {
- fprintf(stderr,"mips memory write error in %s,
addr=0x%x..\n",__FUNCTION__,addr);
+ fprintf(stderr,"mips memory write error in %s,
addr=0x%x,pc=0x%x..\n",__FUNCTION__,addr, mstate->pc);
skyeye_exit(-1);
}
}
@@ -379,7 +382,7 @@
//mbp->write_halfword(state, addr, data);
mips_global_mbp->write_word (addr, v);
} else {
- fprintf(stderr,"mips memory write error..\n");
+ fprintf(stderr,"mips memory write error in
%s,addr=0x%x, pc=0x%x..\n", __FUNCTION__, addr, mstate->pc);
exit(-1);
}
}
Modified: skyeye-v1/trunk/arch/mips/common/tlb.c
===================================================================
--- skyeye-v1/trunk/arch/mips/common/tlb.c 2007-07-07 14:07:00
UTC (rev 268)
+++ skyeye-v1/trunk/arch/mips/common/tlb.c 2007-07-07 14:11:26
UTC (rev 269)
@@ -111,8 +111,8 @@
return 0; // shut up the compiler
} else {
// The physical address is already encoded.
- va = va & ~0x80000000;
region_type = KSEG1;
+ va = va & ~0xE0000000;
return va;
}
} else {
@@ -124,6 +124,7 @@
region_type = KSEG2;
}
}
+ fprintf(stderr, "Warning:Can not find entry for mips tlb in
%s,va=0x%x,pc=0x%x\n",__FUNCTION__, va, mstate->pc);
// Now, we are ready to probe the TLB.
TLBEntry* entry = probe_tlb(mstate, va);
Modified: skyeye-v1/trunk/arch/mips/mach/skyeye_mach_au1100.c
===================================================================
--- skyeye-v1/trunk/arch/mips/mach/skyeye_mach_au1100.c 2007-07-07
14:07:00 UTC (rev 268)
+++ skyeye-v1/trunk/arch/mips/mach/skyeye_mach_au1100.c 2007-07-07
14:11:26 UTC (rev 269)
@@ -35,13 +35,28 @@
/* 2007-01-18 added by Anthony Lee : for new uart device frame */
#include "skyeye_uart.h"
+extern MIPS_State* mstate;
-/* Interrupt Controller */
+typedef struct gpio_ctrl_s{
+ uint32_t sys_trioutrd;
+ uint32_t sys_outrd;
+ uint32_t sys_pininputen;
+ uint32_t sys_outputclr;
+}gpio_ctrl_t;
-/* UART Controller */
+/* Clock Register Descriptions */
+typedef struct sys_clock_s{
+ uint32_t sys_freqctrl0;
+ uint32_t sys_freqctrl1;
+ uint32_t sys_clksrc;
+ uint32_t sys_cpupll;
+ uint32_t sys_auxpll;
+ uint32_t sys_cntrctrl;
+ uint32_t sys_toytrim;
+}sys_clock_t;
-extern MIPS_State *mstate;
+/* UART Controller */
typedef struct uart_s {
uint32_t rxdata;
uint32_t txdata;
@@ -57,6 +72,7 @@
uint32_t enable;
}uart_t;
+/* Interrupt Controller */
typedef struct int_ctrl_s {
uint32_t cfg0rd;
uint32_t cfg0set;
@@ -88,27 +104,33 @@
uint32_t testbit;
}int_ctrl_t;
+typedef struct pm_ctrl_s{
+ uint32_t sys_powerctrl;
+}pm_ctrl_t;
typedef struct au1100_io_s {
uart_t uart;
int_ctrl_t intc;
+ sys_clock_t clock;
+ gpio_ctrl_t gpio_ctrl;
+ pm_ctrl_t pm;
}au1100_io_t;
static au1100_io_t io;
static void
-au1100_io_do_cycle ()
+au1100_io_do_cycle (void * state)
{
}
static UInt32
-au1100_io_read_byte(UInt32 addr)
+au1100_io_read_byte(void * state, UInt32 addr)
{
UInt32 ret;
switch (addr) {
default:
- fprintf("I/O err in %s, addr=0x%x\n",
__FUNCTION__, addr);
+ fprintf(stderr,"I/O err in %s, addr=0x%x\n",
__FUNCTION__, addr);
skyeye_exit(-1);
}
@@ -116,13 +138,13 @@
}
static UInt32
-au1100_io_read_halfword(UInt32 addr)
+au1100_io_read_halfword(void * state, UInt32 addr)
{
UInt32 ret;
switch (addr) {
default:
- fprintf("I/O err in %s, addr=0x%x\n",
__FUNCTION__, addr);
+ fprintf(stderr, "I/O err in %s, addr=0x%x\n",
__FUNCTION__, addr);
skyeye_exit(-1);
}
@@ -130,13 +152,22 @@
}
static UInt32
-au1100_io_read_word(UInt32 addr)
+au1100_io_read_word(void * state, UInt32 addr)
{
UInt32 ret;
switch (addr) {
+ case 0x11900014:
+ ret = io.clock.sys_cntrctrl;
+ break;
+ case 0x1190003c:
+ ret = io.pm.sys_powerctrl;
+ break;
+ case 0x11900060:
+ ret = io.clock.sys_cpupll;
+ break;
default:
- fprintf("I/O err in %s, addr=0x%x\n",
__FUNCTION__, addr);
+ fprintf(stderr, "I/O err in %s, addr=0x%x\n",
__FUNCTION__, addr);
skyeye_exit(-1);
}
@@ -144,39 +175,67 @@
}
static void
-au1100_io_write_byte(UInt32 addr, UInt32 data)
+au1100_io_write_byte(void * state, UInt32 addr, UInt32 data)
{
unsigned char c = data & 0xff;
switch (addr) {
default:
- fprintf("I/O err in %s, addr=0x%x\n",
__FUNCTION__, addr);
+ fprintf(stderr, "I/O err in %s, addr=0x%x\n",
__FUNCTION__, addr);
skyeye_exit(-1);
}
}
static void
-au1100_io_write_halfword(UInt32 addr, UInt32 data)
+au1100_io_write_halfword(void * state, UInt32 addr, UInt32 data)
{
switch (addr) {
default:
- fprintf("I/O err in %s, addr=0x%x\n",
__FUNCTION__, addr);
+ fprintf(stderr, "I/O err in %s, addr=0x%x\n",
__FUNCTION__, addr);
skyeye_exit(-1);
}
}
static void
-au1100_io_write_word(UInt32 addr, UInt32 data)
+au1100_io_write_word(void * state, UInt32 addr, UInt32 data)
{
switch (addr) {
+ case 0x11900000:
+ io.clock.sys_toytrim = data;
+ break;
+ case 0x11900014:
+ io.clock.sys_cntrctrl = data;
+ break;
+ case 0x11900020:
+ io.clock.sys_freqctrl0 = data;
+ break;
+ case 0x11900024:
+ io.clock.sys_freqctrl1 = data;
+ break;
+ case 0x11900028:
+ io.clock.sys_clksrc = data;
+ break;
+ case 0x1190003c:
+ io.pm.sys_powerctrl = data;
+ break;
+ case 0x11900060:
+ io.clock.sys_cpupll = data;
+ break;
+ case 0x11900064:
+ io.clock.sys_auxpll = data;
+ break;
+ case 0x11900110:
+ io.gpio_ctrl.sys_pininputen = data;
+ break;
default:
- fprintf("I/O err in %s, addr=0x%x\n",
__FUNCTION__, addr);
+ fprintf(stderr, "I/O err in %s,
addr=0x%x,pc=0x%x\n", __FUNCTION__, addr, mstate->pc);
skyeye_exit(-1);
}
}
+
static void
au1100_disable_int()
{
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