[Skyeye-developer] Help with cache and MMU models for ARM920T

[Juan Castillo]

Hello everybody.

I wrote some mails before about possibility of measuring cache performance in 
arm920t cores with skyeye.

I have been analysing source code of mmu and caches and I have one question: 
in file "arm920t_mmu.c", the function "arm920t_mmu_read(...)" performs a 
read, but it seems that if you have MMU_Disable (line 244), data is obtained 
directly from bank memory and we return from function. Cache access is 
performed after this condition.

So, it seems that if MMU is disable, caches are also disable. I think that 
arm920t core accesses caches with virtual addresses, so MMU is only neccesary 
when a cache miss occurs. MMU and caches are independent systems that can be 
separately enabled.

Could anybody tell me how the cache model has been obtained? I do not think 
that MMU has to be enabled to use caches, but maybe I am wrong.

Thank you very much.

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